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18 v, precision, micropower cmos rrio operational amplifier ad8657 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features micropower at high voltage (18 v): 18 a typical low offset voltage: 350 v maximum single-supply operation: 2.7 v to 18 v dual-supply operation: 1.35 v to 9 v low input bias current: 20 pa gain bandwidth: 200 khz unity-gain stable excellent electromagnetic interference immunity applications portable operating systems current monitors 4 ma to 20 ma loop drivers buffer/level shifting multipole filters remote/wireless sensors low power transimpedance amplifiers pin configuration out a 1 ?in a 2 +in a 3 v? 4 v+ 8 out b 7 ?in b 6 +in b 5 ad8657 top view (not to scale) 08804-001 figure 1. 8-lead msop 08804-061 ad8657 top view (not to scale) notes 1. it is recommended to connect the exposed pad to v?. 3 +in a 4 v? 1 o ut a 2 ?in a 6 ?in b 5 +in b 8v+ 7out b figure 2. 8-lead lfcsp general description the ad8657 is a dual, micropower, precision, rail-to-rail input/output amplifier optimized for low power and wide operating supply voltage range applications. the ad8657 operates from 2.7 v up to 18 v with a typical quiescent supply current of 18 a. it uses the analog devices, inc., patented digitrim? trimming technique, which achieves low offset voltage. the ad8657 also has high immunity to electromagnetic interference. the combination of low supply current, low offset voltage, very low input bias current, wide supply range, and rail-to-rail input and output makes the ad8657 ideal for current monitoring and current loops in process and motor control applications. the combination of precision specifications makes this device ideal for dc gain and buffering of sensor front ends or high impedance input sources in wireless or remote sensors or transmitters. the ad8657 is specified over the extended industrial tempera- ture range (?40c to +125c) and is available in an 8-lead msop package and an 8-lead lfcsp package. table 1. micropower op amps supply voltage 5 v 12 v to 16 v 36 v single ad8500 ad8663 ada4505-1 ad8505 ad8541 ad8603 dual ad8502 ad8667 op295 ada4505-2 op281 ada4062-2 ad8506 ad8542 ad8607 quad ad8504 ad8669 op495 ada4505-4 op481 ada4062-4 ad8508 ad8544 ad8609
ad8657 rev. a | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? pin configuration ............................................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? electrical characteristics2.7 v operation ............................ 3 ? electrical characteristics10 v operation ............................. 4 ? electrical characteristics18 v operation ............................. 5 ? absolute maximum ratings ............................................................ 6 ? thermal resistance ...................................................................... 6 ? esd caution .................................................................................. 6 ? typical performance characteristics ............................................. 7 ? applications information .............................................................. 17 ? input stage ................................................................................... 17 ? output stage ................................................................................ 17 ? rail to rail ................................................................................... 18 ? resistive load ............................................................................. 18 ? comparator operation .............................................................. 19 ? emi rejection ratio .................................................................. 20 ? 4 ma to 20 ma process control current loop transmitter .................................................................................. 20 ? outline dimensions ....................................................................... 21 ? ordering guide .......................................................................... 21 ? revision history 3/11rev. 0 to rev. a added lfcsp package information ........................... throughout added figure 2, renumbered subsequent figures ................... 1 changes to table 2, introductory text; input characteristics, offset voltage and common-mode rejection ratio test conditions/comments; and dynamic performance, phase margin values ................................................................................... 3 changes to table 3, introductory text; input characteristics, offset voltage and common-mode rejection ratio test conditions/comments .................................................................... 4 changes to table 4, introductory text; input characteristics, offset voltage and common-mode rejection ratio test conditions/comments .................................................................... 5 changes to thermal resistance section and table 5 ................... 6 updated outline dimensions ....................................................... 21 changes to ordering guide .......................................................... 21 1/11revision 0: initial version
ad8657 rev. a | page 3 of 24 sp ecifications electrical character istics 2.7 v operation v s y = 2.7 v, v cm = v sy /2 v , t a = 25c, unless otherwise specified. table 2 . parameter symbol test conditions /comments min typ max unit input characteristics offset vol tage v os v cm = 0 v to 2.7 v 350 v v cm = 0.3 v to 2.4 v; ?40c t a +85c 1 mv v cm = 0.3 v to 2.4 v; ?40c t a +125c 2.5 mv v cm = 0 v to 2.7 v; ?40c t a +125c 4 mv input bias current i b 1 10 pa ? 40c t a +125c 2.6 na input offset current i os 20 pa ?40c t a +125c 500 p a input voltage range 0 2.7 v common - mode rejection ratio cmrr v cm = 0 v to 2.7 v 79 95 db v cm = 0.3 v to 2.4 v ; ?40c t a +85 c 70 db v cm = 0.3 v to 2.4 v ; ?40c t a +125c 63 db v cm = 0 v to 2.7 v ; ?40c t a +12 5c 60 db large signal voltage gain a vo r l = 100 k ?, v o = 0.5 v to 2.2 v 9 4 105 db ?40c t a +85c 75 db ?40c t a +125c 65 db offset voltage drift v os / t 2 v/c input resistance r in 10 g ? input capacitance, differential mode c indm 3.5 pf input capacitance, common mode c incm 3.5 pf output characteristics output voltage high v oh r l = 100 k ? to v cm ; ?40c t a +125c 2.69 v output voltage low v ol r l = 100 k ? to v cm ; ?40c t a +125c 10 mv short - circuit curren t i sc 4 ma closed - loop output impedance z out f = 1 khz, a v = 1 20 ? power supply power supply rejection ratio psrr v sy = 2.7 v to 18 v 105 125 db ?40c t a +125c 70 db supply current per amplifier i sy i o = 0 ma 18 22 a ?40c t a +125c 33 a dynamic performance slew rate sr r l = 1 m ?, c l = 10 p f, a v = 1 38 v/ms settling time to 0.1% t s v in = 1 v step, r l = 100 k ?, c l = 10 pf 14 s gain bandwidth product gbp r l = 1 m ?, c l = 10 p f, a v = 1 170 khz phase marg in m r l = 1 m ?, c l = 10 p f, a v = 1 6 0 degrees channel separation cs f = 10 khz, r l = 1 m ? 105 db emi rejection ratio of +in x emirr v in = 100 mv p eak ; f = 400 mhz , 900 mhz, 1800 mhz, 2400 mhz 90 db noise performance voltage noise e n p - p f = 0.1 hz to 10 hz 6 v p -p voltage noise density e n f = 1 khz 6 0 nv/ hz f = 10 khz 56 nv/ hz current noise density i n f = 1 khz 0.1 pa/ hz
ad8657 rev. a | page 4 of 24 electrical character istics 10 v operation v s y = 10 v, v cm = v sy /2 v , t a = 25c, unless otherwise sp ecified. table 3 . parameter symbol test conditions/comments min typ max unit input characteristics offset voltage v os v cm = 0 v to 10 v 350 v v cm = 0 v to 10 v ; ? 40 c t a +125 c 9 mv input bias current i b 2 15 pa ? 40 c t a +125 c 2.6 na input offset current i os 30 pa ? 40 c t a +125 c 500 p a input voltage range 0 10 v common - mode rejection ratio cmrr v cm = 0 v to 10 v 90 105 db v cm = 0 v to 10 v ; ?40c t a +125c 64 db large si gnal voltage gain a vo r l = 100 k ? , v o = 0.5 v to 9.5 v 105 120 db ? 40 c t a +85 c 95 db ? 40 c t a +125 c 67 db offset voltage drift v os / t 2 v/c input resistance r in 10 g ? input capacitance, differential mode c indm 3.5 pf i nput capacitance, common mode c incm 3.5 pf output characteristics output voltage high v oh r l = 100 k ? to v cm ; ? 40 c t a +125 c 9.98 v output voltage low v ol r l = 100 k ? to v cm ; ? 40 c t a +125 c 20 m v short - circuit current i sc 11 ma closed - loop output impedance z out f = 1 khz, a v = 1 15 ? power supply power supply rejection ratio psrr v sy = 2.7 v to 18 v 105 125 db ? 40 c t a +125 c 70 db supply current per amplifier i sy i o = 0 ma 18 22 a ? 40 c t a +125 c 33 a dynamic performance slew rate sr r l = 1 m ?, c l = 10 p f, a v = 1 6 0 v/ms settling time to 0.1% t s v in = 1 v step, r l = 100 k ?, c l = 10 pf 1 3 s gain bandwidth product gbp r l = 1 m ?, c l = 10 p f, a v = 1 200 khz phase margin m r l = 1 m ?, c l = 10 pf , a v = 1 60 degrees channel separation cs f = 10 khz, r l = 1 m ? 105 db emi rejection ratio of +in x emirr v in = 100 mv peak ; f = 400 mhz , 900 mhz, 1800 mhz, 2400 mhz 90 db noise performance voltage noise e n p - p f = 0.1 hz to 10 hz 5 v p -p voltage noise density e n f = 1 khz 50 nv/ hz f = 10 khz 45 nv/ hz current noise density i n f = 1 khz 0.1 pa/ hz
ad8657 rev. a | page 5 of 24 electrical character istics 18 v operation v s y = 18 v, v cm = v sy /2 v , t a = 25c, unless otherwise specified. table 4 . parameter symbol test conditions/comments min typ max unit input characteristics offset voltage v os v cm = 0 v to 18 v 350 v v cm = 0.3 v to 17.7 v ; ?40c t a +85c 1.2 mv v cm = 0.3 v to 17.7 v ; ?40c t a +125c 2 mv v cm = 0 v to 18 v ; ?40c t a +125c 11 mv input bias current i b 5 2 0 pa ?40c t a +125c 2.9 na input offset current i os 40 pa ?40c t a +125c 500 p a input voltage range 0 18 v common - mode rejection ratio cmrr v cm = 0 v to 18 v 95 110 db v cm = 0.3 v to 17.7 v ; ?40c t a +85c 83 db v cm = 0.3 v to 17.7 v ; ?40c t a +125c 80 db v cm = 0 v to 18 v ; ?40c t a +125c 67 db large signal voltage gain a vo r l = 100 k ?, v o = 0.5 v to 17.5 v 110 120 db ?40 c t a +85c 105 db ?40c t a +125c 73 db offset voltage drift v os / t 2 v/c input resistance r in 10 g ? input capacitance, differential mode c indm 3.5 pf input capacitance, common mode c incm 10.5 pf output characteristics output voltage high v oh r l = 100 k ? to v cm ; ?40c t a +125c 17.97 v output voltage low v ol r l = 100 k ? to v cm ; ?40c t a +125c 3 0 m v short - circuit current i sc 12 ma closed - loop output impedance z out f = 1 khz, a v = 1 15 ? power supply power supply rejection ratio psrr v sy = 2.7 v to 18 v 105 125 db ?40c t a +125c 70 db supply current per amplifier i sy i o = 0 ma 18 22 a ?40c t a +125c 33 a dynamic performance slew rate sr r l = 1 m ?, c l = 10 p f, a v = 1 70 v/ms settling time to 0.1% t s v in = 1 v step, r l = 100 k ?, c l = 10 pf 1 2 s gain bandwidth product gbp r l = 1 m ?, c l = 10 p f, a v = 1 200 khz phase margin m r l = 1 m ?, c l = 10 p f, a v = 1 60 degrees channel separation cs f = 10 khz , r l = 1 m ? 105 db emi rejection ratio of + in x emirr v in = 100 mv peak ; f = 400 mhz , 900 mhz, 1800 mhz, 2400 mhz 90 db noise performance voltage noise e n p - p f = 0.1 hz to 10 hz 5 v p -p voltage noise density e n f = 1 khz 50 nv/ hz f = 10 khz 45 nv/ hz current noise density i n f = 1 khz 0.1 pa/ hz
ad8657 rev. a | page 6 of 24 absolute maximum rat ings table 4 . parameter rating supply voltage 20.5 v input voltage (v ?) ? 300 mv to (v+) + 300 mv input current 1 10 ma differentia l input voltage v sy output short - circuit duration to gnd indefinite temperature range storage ? 65 c to +150 c operating ? 40 c to +125 c junction ? 65 c to +150 c lead temperature (soldering, 60 sec) 300 c 1 the input pins have clamp diodes to t he power supply pins. limit t he input current to 10 ma or less whenever input signals exc eed the power supply rail by 0.3 v. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. t hermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages using a standard 4 - layer j edec board. the exposed pad is soldered to the board. table 5 . ther mal resistance package type ja jc unit 8 - lead msop (rm-8) 142 45 c/w 8 - lead lfcsp (cp -8 -11) 75 12 c/w esd caution
ad8657 rev. a | page 7 of 24 typical performance characteristics t a = 25 c, unless otherwise noted. 20 40 60 80 100 120 140 160 number of amplifiers v sy = 2.7v v cm = v sy /2 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 120 140 v os (v) 08804-002 figure 3 . input offset v oltage distribution 0 2 4 6 8 10 12 14 16 18 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 number of amplifiers tcv os (v/c) v sy = 2.7v ?40c t a +125c 08804-003 figure 4 . input offset voltage drift distribution ?300 ?200 ?100 0 100 200 300 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 v os (v) v cm (v) v sy = 2.7v 08804-004 figure 5 . input offset voltage vs. common - mode voltage 0 20 40 60 80 100 120 140 160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 120 140 number of amplifiers v os (v) v sy = 18v v cm = v sy /2 08804-005 figure 6 . input offset voltage distribution 0 2 4 6 8 10 12 14 18 16 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 number of amplifiers tcv os (v/c) v sy = 18v ?40c t a +125c 08804-006 figure 7 . input offset voltage drift distribution ?300 ?200 ?100 0 100 200 300 0 2 4 6 8 10 12 14 16 18 v os (v) v cm (v) v sy = 18v 08804-007 figure 8 . input offset voltage vs. common - mode voltage
ad8657 rev. a | page 8 of 24 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 v os (mv) v cm (v) v sy = 2.7v ?40c t a +85c 08804-108 figure 9 . input offset voltage vs. common - mode voltage ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 v os (mv) v cm (v) 08804-109 v sy = 2.7v ?40c t a +125c figure 10 . input offset voltage vs. common - mode voltage 0.1 1 10 100 1000 10000 25 50 75 100 125 i b (pa) temper a ture (c) i b + i b ? v sy = 2.7v 08804-008 figure 11 . input bias current vs. temperature ?4 ?2 0 2 4 ?3 ?1 1 3 0 2 4 6 8 10 12 14 16 18 v os (mv) v cm (v) 08804-111 v sy = 18v ?40c t a +85c figure 12 . input offset voltage vs. common - mode voltage ?6 ?4 ?2 0 2 4 6 0 2 4 6 8 10 12 14 16 18 v sy = 18v ?40c t a +125c v os (mv) v cm (v) 08804-112 figure 13 . input offset voltage vs. common - mode voltage 0.1 1 10 100 1000 10000 25 50 75 100 125 i b (pa) temper a ture (c) v sy = 18v 08804-011 i b + i b ? figure 14 . input bias current vs. temperature
ad8657 rev. a | page 9 of 24 ?4 ?3 ?2 ?1 0 1 2 3 4 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 i b (na) v cm (v) 25c 85c 125c v sy = 2.7v 08804-009 figure 15 . input bias current vs. common - mode voltage 0.01m 0.1m 1m 10m 100m 1 10 0.001 0.01 0.1 1 10 100 output vo lt age (v oh ) t o supp l y rai l (v) load current (ma) ?40c +25c +85c +125c v sy = 2.7v 08804-010 figure 16 . output voltage (v oh ) to supply rail vs. load current 0.01m 0.1m 1m 10m 100m 1 10 0.001 0.01 0.1 1 10 100 output vo lt age (v ol ) t o supp l y rai l (v) load current (ma) ?40c +25c +85c +125c v sy = 2.7v 08804-014 figure 17 . output voltage (v ol ) to supply rail vs. load current 0 2 4 6 8 10 12 14 16 18 v cm (v) 25c 85c 125c v sy = 18v 08804-012 ?4 ?3 ?2 ?1 0 1 2 3 4 i b (na) figure 18 . input bias current vs. common - mode voltage 0.01m 0.1m 1m 10m 100m 1 10 output vo lt age (v oh ) t o supp l y rai l (v) load current (ma) ?40c +25c +85c +125c v sy = 18v 0.001 0.01 0.1 1 10 100 08804-013 figure 19 . output voltage (v oh ) to supply rail vs. load current 0.01m 0.1m 1m 10m 100m 1 10 0.001 0.01 0.1 1 10 100 output vo lt age (v ol ) t o supp l y rai l (v) load current (ma) ?40c +25c +85c +125c v sy = 18v 08804-017 figure 20 . output voltage (v ol ) to supply rail vs. load current
ad8657 rev. a | page 10 of 24 2.695 2.696 2.697 2.698 2.699 2.700 ?50 ?25 0 25 50 75 100 125 output vo lt age, v oh (v) temper a ture (c) r l = 100k ? r l = 1m ? v sy = 2.7v 08804-015 figure 21 . output voltage (v oh ) vs. temperat ure 0 2 4 6 8 10 12 ?50 ?25 0 25 50 75 100 125 output vo lt age, v ol (mv) temper a ture (c) r l = 100k ? r l = 1m ? v sy = 2.7v 08804-016 figure 22 . output voltage (v ol ) vs. temperature 0 5 10 15 20 25 30 35 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 i sy per am p (a) v cm (v) ?40c +25c +85c +125c v sy = 2.7v 08804-120 figure 23 . supply current vs. common - mode voltage 17.975 17.980 17.985 17.990 17.995 18.000 ?50 ?25 0 25 50 75 100 125 output vo lt age, v oh (v) temper a ture (c) r l = 100k ? r l = 1m ? v sy = 18v 08804-018 figure 24 . output voltage (v oh ) vs. temperature 0 2 4 6 8 10 12 ?50 ?25 0 25 50 75 100 125 output vo lt age, v ol (mv) temper a ture (c) r l = 100k ? r l = 1m ? v sy = 18v 08804-019 figure 25 . output voltage (v ol ) vs. temperature 0 5 10 15 20 25 30 35 0 3 6 9 12 15 18 i sy per am p (a) v cm (v) ?40c +25c +85c +125c v sy = 18v 08804-123 figure 26 . supply current vs. common - mode voltage
ad8657 rev. a | page 11 of 24 0 5 10 15 20 25 30 35 0 3 6 9 12 15 18 i sy per am p (a) v sy (v) ?40c +25c +85c +125c 08804-020 figure 27 . supply current vs. supply voltage ?135 ?90 ?45 0 45 90 135 ?60 ?20 ?40 0 20 40 60 1k 10k 100k 1m phase (degrees) open-loo p gain (db) frequenc y (hz) v sy = 2.7v r l = 1m ? phase gain 08804-021 c l = 10pf c l = 100pf figure 28 . open - loop gain and phase vs. frequency ?60 ?40 ?20 0 20 40 60 100 1k 10k 100k 1m closed-loo p gain (db) frequenc y (hz) v sy = 2.7v a v = 100 a v = 10 a v = 1 08804-022 figure 29 . closed - loop gain vs. frequency 0 10 20 30 40 50 60 ?50 ?25 0 25 50 75 100 125 i sy per am p (a) temper a ture (c) v sy = 2.7v v sy = 18v 08804-023 figure 30 . supply current vs. temperature 1k 10k 100k 1m open-loo p gain (db) frequenc y (hz) v sy = 18v r l = 1m ? 08804-024 phase c l = 10pf c l = 100pf ?135 ?90 ?45 0 45 90 135 ?60 ?20 ?40 0 20 40 60 gain phase (degrees) figure 31 . open - loop gain and phase vs. fr equency ?60 ?40 ?20 0 20 40 60 100 1k 10k 100k 1m closed-loo p gain (db) frequenc y (hz) v sy = 18v a v = 100 a v = 10 a v = 1 08804-025 figure 32 . closed - loop gain vs. frequency
ad8657 rev. a | page 12 of 24 1 10 100 1000 100 1k 10k 100k z out () frequenc y (hz) v sy = 2.7v a v = 1 a v = 10 a v = 100 08804-026 figure 33 . output impedance vs. frequency 0 20 40 60 80 100 120 140 100 1k 10k 100k 1m cmrr (db) frequenc y (hz) v sy = 2.7v v cm = 2.4v 08804-027 figure 34 . cmrr vs. frequency 0 20 40 60 80 100 100 1k 10k 100k 1m psrr (db) frequenc y (hz) psrr+ psrr? v sy = 2.7v 08804-028 figure 35 . psr r vs. frequency 1 10 100 1000 100 1k 10k 100k z out () frequenc y (hz) v sy = 18v a v = 1 a v = 10 a v = 100 08804-029 figure 36 . output impedance vs. frequency 100 1k 10k 100k 1m cmrr (db) frequenc y (hz) v sy = 18v v cm = v sy /2 0 20 40 60 80 100 120 140 08804-030 figure 37 . cmrr vs. frequency 0 20 40 60 80 100 100 1k 10k 100k 1m psrr (db) frequenc y (hz) psrr+ psrr? v sy = 18v 08804-031 figure 38 . psrr vs. frequency
ad8657 rev. a | page 13 of 24 0 10 20 30 40 50 60 70 10 100 1000 overshoot (%) ca p aci t ance (pf) v sy = 2.7v v in = 10mv p-p r l = 1m ? os+ os? 08804-032 figure 39 . small signa l overshoot vs. load capacitance time (100s/div) voltage (500mv/div) v sy = 1.35v a v = 1 r l = 1m ? c l = 100pf 08804-033 figure 40 . large signal transient response time (100s/div) voltage (5mv/div) v sy = 1.35v a v = 1 r l = 1m ? c l = 100pf 08804-034 figure 41 . small signal transient response 0 10 20 30 40 50 60 70 10 100 1000 overshoot (%) ca p aci t ance (pf) v sy = 18v v in = 10mv p-p r l = 1m ? os+ os? 08804-035 figure 42 . small signal overshoot vs. load cap acitance time (100s/div) voltage (5v/div) v sy = 9v a v = 1 r l = 1m ? c l = 100pf 08804-036 figure 43 . large signal transient response time (100s/div) voltage (5mv/div) v sy = 9v a v = 1 r l = 1m ? c l = 100pf 08804-037 figure 44 . small signal transient response
ad8657 rev. a | page 14 of 24 time (40s/div) ?0.4 ?0.2 0 2 1 0 input voltage (v) output voltage (v) v sy = 1.35 a v = ?10 r l = 1m ? input output 08804-039 figure 45 . positive overload recovery time (40s/div) 0 0.2 0.4 0 ?1 ?2 input voltage (v) output voltage (v) v sy = 1.35v a v = ?10 r l = 1m ? input output 08804-038 figure 46 . negative overload recovery time (10s/div) 0 +5mv ?5mv voltage (500mv/div) v sy = 2.7v r l = 100k ? c l = 10pf input output error band 08804-040 figure 47 . positive settling time to 0.1% time (40s/div) ?1 0 ?2 10 5 0 input voltage (v) output voltage (v) v sy = 9v a v = ?10 r l = 1m ? input output 08804-042 figure 48 . positive overload recovery time (40s/div) 0 1 2 0 ?5 ?10 input voltage (v) output voltage (v) v sy = 9v a v = ?10 r l = 1m ? input output 08804-041 figure 49 . negative overload recovery time (10s/div) 0 +5mv ?5mv voltage (500mv/div) v sy = 18v r l = 100k ? c l = 10pf input output error band 08804-043 figure 50 . positive settling time to 0.1%
ad8657 rev. a | page 15 of 24 time (10s/div) 0 +5mv ?5mv voltage (500mv/div) v sy = 2.7v r l = 100k ? c l = 10pf input output error band 08804-044 figure 51 . negative settling time to 0.1% 1 10 100 1000 10 100 1k 10k 100k 1m volt age noise densit y (nv/ hz) frequenc y (hz) v sy = 2.7v 08804-045 figure 52 . voltage noise density vs. frequency time (2s/div) voltage (2v/div) v sy = 2.7v 08804-046 figure 53 . 0.1 hz to 10 h z noise time (10s/div) 0 +5mv ?5mv voltage (500mv/div) v sy =18v r l = 100k ? c l = 10pf input output error band 08804-047 figure 54 . negative settling time to 0.1% 1 10 100 1000 10 100 1k 10k 100k 1m volt age noise densit y (nv/ hz) frequenc y (hz) v sy = 18v 08804-048 figure 55 . voltage noise density vs. frequency time (2s/div) voltage (2v/div) v sy = 18v 08804-049 figure 56 . 0.1 hz to 10 hz noise
ad8657 rev. a | page 16 of 24 0 0.5 1.0 1.5 2.0 2.5 3.0 10 100 1k 10k 100k 1m output swing (v) frequenc y (hz) v sy = 2.7v v in = 2.6v r l = 1m ? a v = 1 08804-050 figure 57 . output swing vs. frequency 0.01 0.1 1 10 100 10 100 1k 10k 100k thd + n (%) frequenc y (hz) v sy = 2.7v v in = 0.2v rms r l = 1m ? a v = 1 08804-051 figure 58 . thd + n vs. frequency ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 1k 10k 100k channe l se p ar a tion (db) frequenc y (hz) v in = 0.5v p-p v in = 1.5v p-p v in = 2.6v p-p v sy = 2.7v r l = 1m ? a v = ?100 08804-052 r l 1m ? 10k? figure 59 . channel separation vs. frequency 10 100 1k 10k 100k 1m output swing (v) frequenc y (hz) 0 2 4 6 8 10 12 14 16 18 20 v sy = 18v v in = 17.9v r l = 1m ? a v = 1 08804-053 figure 60 . output swing vs. frequency 0.01 0.1 1 10 100 10 100 1k 10k 100k thd + n (%) frequenc y (hz) v sy = 18v v in = 0.2v rms r l = 1m ? a v = 1 08804-054 figure 61 . thd + n vs. frequency ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 1k 10k 100k channe l se p ar a tion (db) frequenc y (hz) v sy = 18v r l = 1m ? a v = ?100 v in = 1v p-p v in = 5v p-p v in = 10v p-p v in = 15v p-p v in = 17v p-p 08804-055 r l 1m ? 10k? figure 62 . channel separation vs. frequency
ad8657 rev. a | page 17 of 24 applications informa tion the ad8657 is a low power, rail - to - rail input and output precision cmos amplifier that operates over a wide supply voltage range of 2.7 v to 18 v. this amplifier uses the analog devices digitrim technique to achieve a higher degree of precision than is available from other cmos amplifiers. the digi t rim techniqu e is a method of trimming the offset volta ge of an amplifie r after assembl y . the advantage of postpackage trim ming is that it corrects any shifts in offset voltage caused by mechanical stresses of assembly. the ad8657 also employs unique input and output stages to achieve a rail - to - rail input and output range wit h a very low supply current. input stage figure 63 shows the simplified schematic of the ad8657. the input st age comprises two differential transistor pairs, an nmos pair (m1, m2) and a pmos pair (m3, m4). the input common - mode vo ltage determines which differential pair turns on and is more active than the other . the pmos differential pair is active when the input voltage approaches and reaches the lower supply rail. the nmos pair is needed for input voltages up to and including t he upper supply rail. this topology allows the amplifier to maintain a wide dynamic input voltage range and to maximize signal swing to both supply rails. for the majority of the input common - mode voltage range, the pmos differ ential pair is active. differ en tial pairs commonly exhibit different offset voltages. the handoff from one pair to the other creates a step - like characteristic that is visible in the v os vs. v cm graph ( see figure 5 and figure 8 ) . thi s is inherent in all rail - t o - rail amplifiers that use the dual differential pair topology. therefore, always choose a common - mode voltage that does not include the region of handoff from one input differential pair to the other. additional steps in the v o s vs. v cm curves are also visible as the input common - mode voltage approaches the power supply rails. these changes are a result of the load transistors (m8, m9, m 14, and m15) running o ut of headroom. as the load transistors are forced into the triode regi on of operation, the mismatch of their drain impedances contributes to the offset voltage of the amplifier. this problem is exacerbated at high temperatures due to the decrease in the threshold voltage of the input transistors (see figure 9 , figure 10, figure 12 , and figure 13 for typical perfor - mance data ). current source i1 drives the pmos transistor pair. as the input common - mode voltage approaches the upper rail , i1 is steered away from the pmos differential pair through the m5 transistor . the bias voltage, vb1, controls the point where this transfer occurs. m5 diverts the tail current in to a current mirror consisting of the m6 and m7 transistors . the output of the current mirror then drives the nmos pair. note that the activation of this current mirror causes a slight increase in supply current at high common - mode vo ltages ( see figure 23 and figure 26 for more details ) . the ad8657 achieves its high performance by using low voltage mos devices for its differential inputs. these low voltage mos devices offer excellent noise and bandwi dth per unit of current. each differe ntial input pair is protected by proprietary regulation circuitry (not shown in the simplified sch ematic). the regula - tion circuitry consists of a combination of active devices that maintain t he pro per voltages across the input pairs during normal operation and passive clamping devices that protect the amp lifier during fast transients. however, t hese passive clamping devices begin to forward bias as the common - mode voltage approa ches either pow er supply rail. this causes an increase in the input bias current (see figure 15 and figure 18) . the input devices are also protected from large differ ential input voltages by clamp diodes ( d1 and d2 ) . th ese diodes are buffered from the inputs with two 10 k ? resistors (r1 and r2). the differential diodes turn on whenever the differential voltage exceeds approx imately 600 mv; in this condition, the differential input resistance drops to 20 k ? . output stage the ad8657 features a complementary output stage consisting of the m16 and m17 transistors. these transistors are configured in class a b topology and are biased by the voltage source , vb2 . this topology allows the output voltage to go within mill i v olts of the supply rails, achieving a rail - to - rail output swing. the output voltage is limited by the output impedance of the transistors, which are low r on mos devices. the output voltage swing is a function of the load current and can be estimated using the outp ut voltage t o the supply rail vs. load current diagrams (see figure 16, figure 17, figure 19, and figure 20) .
ad8657 rev. a | page 18 of 24 v+ v? +in x r1 d1 d2 m1 m2 m7 m6 m3 m4 m5 vb1 m8 m10 m9 m16 m17 m1 1 vb2 out x m12 m14 m13 m15 i1 r2 ?in x 08804-056 figure 63 . si mplified schematic rail to r ail the ad8657 features rail - to - rail input and output with a supply voltage from 2.7 v to 18 v. figure 64 shows the input and output waveforms of the ad8657 configured as a unity - gain buf fer with a sup ply voltage of 9 v and a resistive load of 1 m ? . with an input voltage of 9 v, the ad8657 allows the output to swing very close to both rails. additionally, it does not exhibit phase reversal. time (200s/div) voltage (5v/div) v sy = 9v r l = 1m ? 08804-057 input output figure 64 . rail - to- rail input and output resistive l oad the f eedback resistor alters the load resistance that an amplifier sees. it is, therefore, important to be aware of the value of feed - bac k resistors chosen for use with the ad8657. the ad8657 is capable of driving resistive load s down to 100 k ? . the following two examples, inverting and noninverting configurations , show how the feedback resistor changes the actual load resistance seen at the output of the amplifier. inverting configuration figure 65 shows ad8657 in a n inverting configuration with a resistive load, r l , at the output. the actual load seen by the amplifier is the parallel combination of the feedback resistor, r2 , and load , r l . having a feedback resistor of 1 k ? and a load of 1 m ? results in an equivalent load resistance of 999 ? at the output. in this condition, the ad8657 is incapable of driving such a heavy load ; therefore, its performance degrades greatly. to avoid loading the output, use a larger feedback resistor , but consider the resistor thermal no ise effect on the overall circuit. ad8657 1/2 r1 r2 r l ?v s y r l, eff = r l || r2 +v sy v in v out 08804-058 figure 65 . inverting op amp noni nverting configuration figure 66 shows the ad8657 in a noninverting configuration with a resistive load, r l , at the output. the actual load seen by the amplifier is the parallel combination of r1 + r2 and r l . r1 r2 r l ?v sy r l, eff = r l || (r1 + r2) +v sy v in v out 08804-059 ad8657 1/2 figure 66 . noninverting op amp
ad8657 rev. a | page 19 of 24 comparator operation op amps are designed to operate in a closed - loop configuration with feedback from its output to its inverting input. figure 67 shows the ad8657 c onfigured as a voltage follower with an input voltage that is always kept at midpoint of the power supplies. the same configuration is applied to the unused channel . a1 an d a2 indicate the placement of ammeters to measure supply current. i sy + refers to the current flowing from the upper supply rail to the op amp, and i sy ? refers to the current flowing from the op amp t o the lower supply rail. as shown in figure 68 , as expected, in normal operating condition, the total current flowing into the op amp is equivalent to the total curr ent flowing out of the op amp, where, i sy + = i sy ? = 36 a for the dual ad8657 at v sy = 18 v . ad8657 1/2 a1 100k? 100k? i sy + +v sy v out ?v sy i sy ? a2 08804-066 figure 67 . voltage follower 0 5 10 15 20 25 30 35 40 0 2 4 6 8 10 12 14 16 18 i sy per dua l amplifier (a) v sy (v) i sy ? i sy + 08804-067 figure 68 . supply current vs. supply voltage (voltage follower) in contrast to o p amps, comparato rs are designed to work in an open - loop configuration and to drive logic circuits. although op a mps are different from comparators, occasionally an unused section of a dual op amp is used as a comparator to save board space and cost ; h owev er, this is not recommended. figure 69 and figure 70 show the ad8657 configured as a com - parator, with 100 k ? resistors in series with the input pin s. any unused channels are configured as buffers with the input voltage kept at the midpoint of the power supplies. the ad8657 has input devices that are protected from large differential input voltages by diode d1 a nd diode d2 (r efer to figure 63) . these diodes consist of substrate pnp bipolar transistors, and conduct whenever the differenti al input voltage exceeds approximately 600 mv ; how - ever, t hese diodes also allow a current path from the input to the lower supply rail, thus resulting in an increase in the total supply current of the system. as shown in figure 71 , both configurations yield the same result. at 18 v of power supply, i sy + remains a t 36 a per dual amplifier, but i sy ? increases to 140 a in magni - tude per dual amplifier. ad8657 1/2 a1 100k? 100k? i sy + +v sy v out ?v sy i sy ? a2 08804-068 figure 69 . comparator a ad8657 1/2 a1 100k? 100k? i sy + +v sy v out ?v sy i sy ? a2 08804-069 figure 70 . comparator b 0 20 40 60 80 100 120 140 160 0 2 4 6 8 10 12 14 16 18 i sy per dua l amplifier (a) v sy (v) i sy ? i sy + 08804-070 figure 71 . supply current vs. suppl y voltage (ad8657 as a comparator) n ote that 100 k ? resistors are used in series with the input of the op amp. if smaller resistor values are used, the supply current of the system increase s much more. for more details on op amps as comparators, refer to t he an - 849 application note using op amps as compa ra tors .
ad8657 rev. a | page 20 of 24 emi rejection r atio circuit performance is often adversely affected by high frequency electro magn etic interference (emi). in the event where signal strengt h is low and transmission lines are long, an op amp must accurately amplify the input signals. however, all op amp pins th e non inverting input, inverting input, positive supply, negative supply , and output pins are susceptible to emi signals. these high fr equen c y signals are coupled into an op amp by various means such as conduction, near field radiation, or far field rad i - ation. for instance, wires and pcb traces can act as antennas and pick up high frequency emi signals. precision op amps, such as the ad 8657, do not amplify emi or rf signals because of their relatively low ban dwidth. however, due to t he non linearities of the input devices, op amps can rectify these out - of - band signals. when these high frequency signals are rectified, they appear as a dc o ffset at the output. to describe the ability of the ad8657 to perform as intended in the presence of an electromagnetic energy, the e lectromagnetic i nterference r ejection ratio (emirr) of the non inverting pin is specified in table 2 , table 3 , and table 4 of the sp ecifications section . a mathematical method of mea suring emirr is defined as follows: emirr = 20 log ( v in_peak / v os ) 20 40 60 80 100 120 140 10m 100m 1g 10g emirr (db) frequenc y (hz) v in = 100mv peak v sy = 2.7v t o 18v 08804-071 figure 72 . emirr vs. frequency 4 m a to 20 m a process control cu rrent loop transmitter the 2 - wire current transmitters are o ften used in distributed control systems and process control applications to transmit analog signa ls between sensors and process controllers. figure 73 shows a 4 ma to 20 ma current loop transmitter. the transmitter powers directly from the control loop power supply , and the current in the loop carries signal from 4 ma to 20 ma. thus, 4 ma establishes the baseline current budget within which the circuit must operate. using the ad8657 is an excellent choice due to its low supply current of 33 a per amplifier over tempera ture and supply voltage. the current transmitter controls the current flowing in the loop, where a zero - scale input signal is represented by 4 ma of current and a full - scale input signal is represented by 20 ma. the transmitte r also floats from the control loop power supply, v dd , while signal ground is in the receiver. the loop current is measured at the load resistor, r l , at the receiver side. with a zero - scale input, a current of v ref /r null flows through r ?. this creates a c urrent flowing through the sense resistor, i sense , determined by the following equation (see figure 73 for details) : i sense, min = ( v ref r ? )/( r null r sense ) with a full - scale input voltage, current flowing through r ? is increa sed by the full - scale change in v in /r span . this creates an increase in the current flowing through the sense resistor. i sense, delta = ( full - scale change in v in r ? )/( r span r sense ) therefore i sense, max = i sense, min + i sense, delta when r ? >> r sense , the current through the load resistor at the receiver side is almost equivalent to i sense . figure 73 is designed for a full - scale input voltage of 5 v. at 0 v of input, loop current is 3.5 ma, and at a full scale of 5 v, the loop current is 21 ma. this allows software calibration to fine tune the current loop to the 4 ma to 20 ma range. the ad8657 and adr125 both consume only 16 0 a quiescent current, making 3.34 ma current available to power additional signal conditioning circuitry or to power a bridge circuit. r l 100? v dd 18v c2 10f c3 0.1f c1 390pf c4 0.1f r4 3.3k ? q1 d1 4ma to 20ma r3 1.2k ? r null 1m ? 1% v ref r span 200k? 1% v in 0v to 5v r1 68k? 1% r2 2k? 1% notes 1. r1 + r2 = r. 1/2 ad8657 c5 10f r sense 100? 1% 08804-060 v out gnd adr125 v in figure 73 . 4 ma to 20 ma current loop transmitter
ad8657 rev. a | page 21 of 24 outline dimensions complian t to jedec standa rds mo-187 -aa 100 709-b 6 0 0.80 0.5 5 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 copla narity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 74 . 8 - lead mini sma ll outline package [msop] (rm - 8) dimensions shown in millimeters 2.44 2.34 2.24 t op view 8 1 5 4 0.30 0.25 0.20 b o t t o m v i e w pin 1 index area sea ting plane 0.80 0.75 0.70 1.70 1.60 1.50 0.203 ref 0.05 max 0.02 nom 0.50 bsc e x p o s e d p a d 3.10 3.00 sq 2.90 pin 1 indica t or (r 0.15) for prope r connection of the exposed pad, refer to the pin confi guration and function descr iptio ns secti on of this data sheet. coplanarity 0.08 0.50 0.40 0.30 compliant t o jedec stand ards mo-229-weed 01-24-201 1-b figure 75 . 8 - lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, very very thin, dual lead (cp - 8 - 11) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding AD8657ARMZ ?40c to +125c 8 - lead m ini s mall o utline p ackage [msop] rm - 8 a2n AD8657ARMZ -r7 ?40c to +125c 8 - lead m ini s mall o utline p ackage [msop] rm - 8 a2n AD8657ARMZ -rl ?40c to +125c 8 - lead m ini s mall o utline p ackage [msop] rm - 8 a2n ad8657a cp z -r7 ?40c to +125c 8 - lead lead frame chip scale p ackage [lfcsp _wd ] cp -8 -11 a2n ad8657a cp z -rl ?40c to +125c 8 - lead lead frame chip scale p ackage [lfcs p_wd ] cp -8 -11 a2n 1 z = rohs compliant part.
ad8657 rev. a | page 22 of 24 notes
ad8657 rev. a | page 23 of 24 not es
ad8657 rev. a | page 24 of 24 notes ? 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08804 - 0 - 3/11(a)

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